The microarchitecture of a router within an interconnect fabric may be the most significant factor impacting the fabric's bandwidth and latency characteristics. Some router designs may incorporate a bus shared among a plurality of ports. Each port may request access to the shared bus in order to place an inbound transaction on the bus and transmit it to another port. If multiple ports simultaneously request access to the shared bus, a centralized arbiter may arbitrate between the requesting ports and grant access to the shared bus one port at a time. Since all ports must arbitrate for access to the single shared bus, the router is limited to transferring only one “chunk” of data (e.g., one unit of data) in any particular clock cycle. For such a “shared-bus backbone,” the bandwidth of the router may be limited to one “chunk” per clock cycle.